1. Field of the Invention
The present invention relates to a non-volatile ferroelectric memory device, and more particularly, a non-volatile ferroelectric memory device having the structure in which a plurality of memory cells of a 1-capacitor and 1-transistor type are arranged, and a function to prevent leakage current from the capacitors.
2. Description of Related Art
First, the general structure and general operation principle of a non-volatile ferroelectric memory device will be described below with reference to FIGS. 1A and 1B.
FIG. 1A is a block diagram of one of a plurality of memory cells of the non-volatile ferroelectric memory device. FIG. 1B is a cross sectional view of such a memory. Referring to these figures, a memory cell MC includes a capacitive element C and a transistor T. The capacitive element C is constructed to sandwich a ferroelectric film FE between two electrodes EL1 and EL2 opposing to each other. The electrode EL1 is connected to a plate line PL and the electrode EL2 is connected to one of the source and drain regions (S/D) of the transistor T. The other of the source and drain regions (S/D) is connected to a bit line BL. The gate of the transistor T is connected to a word line WL.
Next, in the ferroelectric film, spontaneous polarization has been generated and the polarization characteristic curve when an electric field is applied externally to the ferroelectric film FE represents a hysteresis curve, as shown in FIG. 2A. When the external electric field is removed, two stable points exist on the polarization curve due to the hysteresis characteristic, as shown as A and C in FIG. 2A. Therefore, the capacitive element C shown in FIG. 1A can hold a binary data when the ferroelectric film FE can be used as a dielectric film of the capacitive element. Further, the capacitive element C can continue to hold the binary data even after the power is disconnected or the electric field is removed. That is, the capacitive element is non-volatile.
In order to change the polarization state from the state A to the state C, it is required that a positive electric field larger than the coercive electric field Ec of the ferroelectric film FE is applied to the ferroelectric film FE in a positive direction. This is accomplished in the example shown in FIGS. 1A and 1B, by setting the word line WL to a high level so that the transistor T is turned on and further by applying a positive electric field larger than the coercive electric field Ec of the ferroelectric film FE in a positive direction between the bit line BL and the plate line PL. On the contrary, in order to change the polarization state from the state C to the state A, it is required that a negative electric field larger than the coercive electric field Ec in a negative direction is applied to the ferroelectric film FE.
In order to read a data held in the capacitive element C, it is required that the transistor T is turned on and a positive electric field Emax is applied to the ferroelectric film FE between the bit line BL and the plate line PL. In this case, when the capacitive element C is in the state A, charge corresponding to (Pmax+Pr) can be taken out as the data held in the state A, whereas, when the capacitive element C is in the state C, charge corresponding to (Pmax-Pr) can be taken out as the data held in the state C. By sensing the charge taken out from state A or C, the data held in the capacitive element C can be determined. In this case, this read operation is destructive to the data held in the state A. Therefore, it is necessary to apply the negative electric field --Emax to the ferroelectric film FE to rewrite the data to the capacitive element C after data is determined to be the data held in the state A.
As shown in FIG. 2B, when the ferroelectric film FE has the film thickness of d, and a voltage of V is applied between electrodes EL1 and EL2, there is relation V=E.times.d between the voltage V and an electric field E applied to the capacitive element C. Accordingly, a voltage corresponding to the coercive electric field is Vc=Ec.times.d. Further, in a case where a non-volatile ferroelectric memory device in which a plurality of memory cells MC are contained therein is typically driven with a single power source, the state D (--Emax) is made to correspond to the lower logic level of a binary data and the state B is made to correspond to the higher logic level of the binary data.
A conventional non-volatile ferroelectric memory device of a single power source driving type has a memory cell array 1x in which a plurality of memory cells MC are arranged, as shown in FIG. 3. In the memory cell array 1x, each of the memory cells MC includes a capacitive element C and a transistor T. The capacitive element C is constituted of a ferroelectric film sandwiched between electrodes opposing to each other. One of the electrodes of the capacitive element C is connected to one of the source and drain regions of the transistor T and the other is connected to a plate line PL1. The other of the source and drain regions of the transistor T is connected to a bit line BL (BL11, . . . , BL2n). The gate of transistor T is connected to a word line WL (WL1, WL2, . . . ). The word lines WL1 and WL2 are also connected to the gates of transistors T41 and T42. One electrode of each transistor T41 or T42 is commonly connected to a plate line PL1 and the other electrode of each transistor is commonly connected to a plate line potential supplying line PL.
Next, the read operation of the above conventional non-volatile ferroelectric memory device will be described below with reference to a waveform diagram of FIG. 4.
The bit line pair BL11 and BL21 and the plate line PL1 are set to the ground potential level in a standby state before the word line WL1 rises to a selection level (high level). When the word line WL1 is set to the selection level, the memory cells MC connected to the word line WL1 are changed to a selectable state. The transistor T41 is also turned on to be in the conductive state, so that the plate line is driven. That is, the plate line potential V.sub.PL is supplied to the plate line PL1 through the transistor T41. As a result, data stored in the memory cells MC are read out onto the first bit lines BL11 to BL1n, respectively. In this case, since the word line WL2 is in the non-selection level so that the memory cells MC connected to the word line WL2 are also in the non-selection state, the potential levels of the bit lines BL21 to BL2n do not almost change. A potential difference between the bit lines BL11 and BL21 of a pair, to BL1n and BL2n of each of bit line pairs is amplified by a sensing amplifier (not shown). The same is true for the other bit line pairs. As a result, the data stored in the memory cells in the selectable state can be read out. (See "FA 16.2: A 256 kb Nonvolatile Ferroelectric Memory at 3 V and 100 ns" by Sumi et al., (IEEE International solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 268-269, 1994)) In this reference, the memory capacity has the capacity of 256 Kb and an access cycle time of 200 ns can be accomplished under the condition of power supply voltage of 3.0 V and consumption current of 3 mA.
In the non-volatile ferroelectric memory device, data can be stored in the memory cell MC by applying an electric field to the ferroelectric film to induce polarization, and the data can be read out by sensing the induced polarization. For this reason, it is necessary to supply a predetermined voltage to a plate line as described above. In addition, the capacitance of the capacitive element C is greater than that of a capacitor in a normal DRAM. Therefore, in the non-volatile ferroelectric memory device, it takes a long time to drive the plate line and it is difficult to operate the memory device at a high speed. For instance, in a case of normal DRAM having the memory capacity of 64 Mb, an access cycle time of 90 ns can be accomplished. In addition, since the plate line is charged and discharged, the power consumption increases.
Next, the circuit diagram of an example of conventional non-volatile ferroelectric memory device is shown in FIG. 5 in which the potential of plate line is fixed. Such an example is disclosed in a Japanese Laid Open Patent Disclosure (JP-A-Hei2-110895).
This non-volatile ferroelectric memory device includes a memory cell array 1y having the same arrangement as in the above-described first conventional memory device except that a plurality of plate lines (PL1, . . . ) are integrated into a common plate line PL. Note that only the two memory cells and pair of bit lines BL11 and BL21 are shown in the figure. Also, the non-volatile ferroelectric memory device includes a plurality of sense amplifiers SA (SA1, . . . ) for each amplifying a potential difference between bit lines of each of pairs such as BL1 and BL2 at a predetermined timing in accordance with control signals SEP and SEN, a precharge circuit 106 for precharging bit lines (BL1, BL2, . . . ) to an intermediate potential level in response to a bit line precharge signal BLP, and an intermediate potential generating circuit 105 for generating an intermediate potential between a logic "1" level and a logic "0" level and supplying the generating potential to the precharge circuit 106 and the plate line PL. The memory device further includes a reference level generating circuit 107 which sets the potentials of bit lines (BL11, BL21, . . . ) to a ground potential level in response to a bit line potential setting signal BLST immediately before one of the word lines, e.g., WL1 changes to a selection level, and supplies a reference level to the bit lines. One corresponding to a selected word line of dummy word lines DWL (DWL1, DWL2, . . . ) to which dummy memory cells are respectively connected is set in the selection level in synchronous with the transit of the selected word line to the selection level and data stored in the memory cell MC is read out on the bit line.
Next, the read operation of the above non-volatile ferroelectric memory device will be described below with reference to FIGS. 6A through 6H.
In a standby state before the memory cell MC is accessed, pairs of bit lines (BL11 and BL21, . . . ) are precharged to an intermediate potential which is substantially the same as that of the plate line PL, as shown in FIG. 6H. For simplification of description, only the pair of bit lines BL11 and BL21 will be described below.
Immediately before the word line WL1 is set in the selection level after access starts, the bit line potential setting signal BLST becomes active as shown in FIG. 6C so that the bit lines BL11 and BL21 are set to the ground potential level as shown in FIG. 6H. Alternatively, the potential may be a power source potential level. Then, the word line WL1 and the dummy word line DWL1 are changed to the selection level as shown in FIGS. 6B and 6C so that the stored information in the selected memory cell MC is read out to the bit line BL21 as shown in FIG. 6H. At this time, the reference level is supplied from the reference level generating circuit 107 to the bit line BL21. Thereafter, like the conventional DRAM, the potential difference between the bit lines BL11 and BL21 is sensed and amplified by the sense amplifier SA1 to be output externally, as shown in FIG. 6H.
In this standby state, if the transistor T of the memory cell MC is in the off state so that a cell node Nmc between the capacitive element C and the transistor T is in a floating state, there is a leakage current between the cell node Nmc and the substrate or well in which the transistor T is formed, although the level of leakage current is very low. The leakage between the cell node and the substrate/well of the ground potential level or power source level makes the potential of cell node Nmc set in the ground potential level or the power source level finally, resulting in inversion of spontaneous polarization of the memory cell MC. For this reason, in this example, the transistor T is slightly turned on by setting the potential level of the word lines WL1, . . . to an intermediate level between the selection level and the non-selection level, so that the charge leaked from the cell node Nmc to the substrate/well is compensated from the bit line. As a result, the potential of cell node Nmc is kept in substantially the same intermediate potential as that of the plate line such that the inversion of spontaneous polarization can be prevented. In this example, the reference level of the bit line is set by the reference level generating circuit 107. However, the way in the first example may be applied.
As described above, in the conventional non-volatile ferroelectric memory device, the plate line is driven to a predetermined level for every access, as shown in the first example. Therefore, a long time is required to drive the plate line. As a result, it is difficult to operate the memory device at a high speed. In addition, the power consumption is increased for charging and discharging of the plate line. In the second example, since a predetermined potential is always supplied to the plate line, there is no problem as in the first example. However, in order to prevent the inverse of spontaneous polarization because of the leakage of charge from the cell node to the substrate/well, it is necessary that a transistor is slightly turned on by setting the word line in a predetermined level between the selection level and the non-selection level, so that the leakage of charge from the cell node is compensated from the bit line to keep the potential of cell node in the substantially the same potential as that of the plate line. In this case, the control of word line potential is complicated and there is a case that a transistor of the memory cell is not turned on because of the dispersion of manufactured devices in characteristic. As a result, the leak cannot be compensated so that the spontaneous polarization may be inverted.